Test Pattern Generation for Transition Faults with Low Power using BS-LFSR and LOC

Abstract

Transition fault testing is widely practiced in industry due to reduce or manage the fault count in IC and reduce the switching transition to reduce the power consumption. By merging of the test cubes from the test generation the low power test patterns are achieved for transition faults. In this paper two techniques named as BS-LFSR and Launch-Off-Capture (LOC) test are analyzed based on area, power, and delay for transition faults. In BS-LFSR, which generate Pseudo-Random pattern with reduced switching transition that occur in the output stream of LFSR, so because of transition reduction low power test generation achieved. In launch-off-capture test, the controllability of the transition fault testing is increased with low power manner. Experimental results for ISCAS’89 S27 benchmark circuits proves which technique is better than the existing technique by reducing power and also compare the area and delay.